The switching speed and power consumption of semiconductor devices are closely linked to line and junction resistances within the semiconductor device. In order to reduce the line resistances, the connecting lines within the semiconductor device are provided from metals. In the case of field effect transistors, the junction resistance between the source/drain regions formed within a monocrystalline semiconductor substrate and a metallized contact structure that bears on the semiconductor substrate and connects the source/drain region to connecting lines formed in a metallization level above the semiconductor substrate remains critical. In order to reduce the junction resistance, the metal silicide is formed along the junction areas between the silicon substrate and the contact structure, the electrical resistance of said metal silicide being lower than that of a silicon/metal junction.
A suitable metal silicide is cobalt silicide. For the purpose of siliciding (silicidation), a cobalt layer is applied to the silicon substrate and subjected to heat treatment at a silicidation temperature of approximately 550 degrees Celsius. Sections of the cobalt layer that adjoin the silicon substrate react with the silicon of the silicon substrate to form cobalt monosilicide. Unreacted sections of the cobalt layer are removed.
During the siliciding, the formation of poorly conducting cobalt oxide at the surface of the cobalt layer and also the formation of cobalt silicide agglomerates can occur even in pure nitrogen environment due to oxygen that outdiffuses from the substrate. Therefore, the cobalt layer is covered by an oxidation protection layer prior to silicidation. For the oxidation protection layer, a material is chosen which reacts more readily with the oxygen than the cobalt, or which is impermeable to oxygen in sputtered form, for instance titanium or titanium nitride. After the silicidation, the oxidation protection layer is removed together with the surplus sections of the cobalt layer.
The removal of the oxidation protection layer and of the surplus cobalt usually includes a sequence of different etching processes, since during the heat treatment, intermediate compounds or alloys comprising the material of the oxidation protection layer and the cobalt layer arise, the removal of which makes it necessary to change the etching solution.
If the oxidation protection layer is provided from titanium, then the first step involves carrying out an etch using an SC1 solution and the second step involves carrying out an etch using an SOPM solution. The SC1 solution (RCA standard clean 1) contains deionized water H2O, hydrogen peroxide H2O2 and ammonium hydroxide typically in the ratio 50:2:1 and is employed at temperatures of between 25 and 70 degrees Celsius.
The SOPM solution (sulfuric ozone peroxide mixture) contains sulfuric acid H2SO4 and hydrogen peroxide H2O2 in the ratio of 84:1, for example, and is enriched with more than 100 g/m3 of ozone. A typical application temperature is 100 degrees Celsius. The designations SPM solution (sulphuric acid peroxide mixture) and piranha solution are customary for a mixture containing sulfuric acid (H2SO4) and hydrogen peroxide (H2O2).
If the oxidation protection layer includes titanium nitride, then a first etch using an SC1 solution is followed, in the second step, by an etch using an SC2 solution, which may be followed by a renewed etch using an SC1 solution in a third step.
The SC2 solution (RCA standard clean 2) contains deionized water H2O, hydrogen peroxide H2O2 and hydrochloric acid HCl typically in the ratio of 20:1:1 and is typically used at temperatures of between 20 and 70 degrees Celsius.
The gate electrodes of the field effect transistors include a doped polysilicon layer in a section adjoining the gate dielectric. In transistor arrangements such as are customary for memory cell arrays, for instance, the gate electrodes of the selection transistors of a plurality of memory cells that are electrically connected in parallel form sections of a contiguous connecting line (word line) via which a group of memory cells are in each case addressed. In order to reduce the electrical line resistance of such a word line, the gate electrodes are provided with an additional low-resistance metal layer bearing on the doped polysilicon layer of the gate electrode. The material of the metal layer is usually tungsten. The metal layer is usually covered by a cap layer, for example a silicon nitride cap.
After the formation of a gate electrode and the source/drain regions of a transistor, an interlayer dielectric (ILD), usually a borophosphosilicate glass (BPSG), is applied to the semiconductor substrate, which covers the semiconductor substrate and the gate electrode. Above the interlayer dielectric, connecting lines between the components formed in the semiconductor substrate are formed in a metallization level. Before the connecting lines are formed, the interlayer dielectric is opened above the source/drain regions to be connected and the gate electrodes. Native silicon oxide that forms on the silicon surface of the source/drain regions is removed by means of a buffered oxide etch (BOE solution) using an etching solution containing NH4F and HF. Contact structures that connect the source/drain regions and gate electrodes, respectively, to the connecting structures to be formed in the further procedure in the metallization level are introduced into the openings.
The silicidation is performed after the cleaning of the silicon surfaces of the source/drain regions using the BOE solution. The silicidation may alternatively be effected as a self-aligned process prior to the deposition of the interlayer dielectric (salicidation, self-aligned silicidation).
In both cases, the cobalt layer also bears in sections on the metal layer of the gate electrode.
During the removal of the oxidation protection layer and the unreacted cobalt, the metal layer is exposed to the etching liquid. When using a piranha solution as the etching liquid, the tungsten is incipiently etched and the tungsten layer is damaged, with the result that the electrical resistance of the tungsten layer is increased.